Job
Description
As a DFT Engineer, you will be implementing state-of-the-art designs in test access mechanisms, scan design (compression, scan rules checking, construction, ATPG vector generation and validation), memory BIST, IOBIST and DFT design for system debu
Requirements:
Bachelor s degree in Computer Science, Electrical Engineering or related fields and at least 2-5 years of related professional experience. Master s degree in Computer Science, Electrical Engineering or related fields with 1-3 years of professional experience.
Experience in implementing scan test plans, BIST for memories and IOs, fault modeling, ATPG and fault simulation
Analytical skills in verification and validation of test patterns and logic on complex and multi-million gate designs using vendor tools
Experience with Mentor/Siemens Tessent
Exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade-offs
Programming and scripting skills in Perl, Python or TCL